A network processing device uses a series of different stages to process incoming and outgoing data packets when the packets are arriving or are exiting the network device. For example, one stage may handle packet header processing, another may handle Medium Access Control (MAC) layer processing, yet another stage may handle Point to Point Protocol (PPP) processing and still another stage may handle High Level Data Link Control (HDLC) processing. Because these different network processing stages receive and process data at different data speeds, oftentimes a series of controlled First In-First Out (FIFO) buffers or queues are used between the different processing stages to help the data flow smoothly and timely through the network device.
Having FIFO queues helps data flow in a timely way through the network device. For example, the presence of a FIFO queue between two processing stages allows the stages to operate in different clock domains, i.e., to operate at different clock speeds, or to operate with clocks at the same speed but not synchronized to one another. By having a FIFO queue between stages with different clock domains, stages do not need to coordinate a data transmission from one stage to another. Instead, after completing its processing, the first stage simply deposits the packet on which it has just completed processing into the FIFO queue and notifies the second stage that the packet is now present in the queue. The second stage then retrieves the packet from the FIFO queue and begins processing the packet. This system uses less time than if the FIFO queues had to transfer data directly from one to the other.
A second reason for having FIFO queues between stages is that it is sometimes impossible to synchronize a single clock signal across a large number of different circuits or stages, due to capacitive loading, signal driving capabilities, etc., and therefore FIFO queues are used to isolate stages and allow them to operate relatively independently from one another.
Data arriving at a network processor generally does not arrive at regular intervals and, in fact, may arrive in sporadic chunks. Also, sometimes one or more of the network processing stages can have a short delay and data behind that stage becomes blocked. These types of data throughput inconsistencies can leave packets of data languishing in one or more of the FIFOs. If the data packets wait too long, the network device may drop one or more of the packets. When one of the stage processes has no data packets to process, it stops processing and waits for the next packet to be delivered to the FIFO queue, after which it receives a signal from the previous stage that data has been deposited in the FIFO queue, and the previously stopped stage starts running again. For this reason these processes are often called run and stop processes, and together the series of processes are known as the run and stop pipeline. These intermittent data transmissions cause delays in processing data in the network processing device, and generally lower performance of the network device.
The present invention addresses these and other problems associated with the prior art.